Achilleas Tsitsimelis

• 2:47PM Nov 05, 2018
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Achilleas Tsitsimelis received his Diploma in Electrical and Computer Engineering from National Technical University of Athens in 2013. His focus was on Electric Energy Systems and Electric Machines. After his graduation, he worked as a research assistant in the Smart Grids Research Unit of the Electrical and Computer Engineering School where his main research interests lied in the field of control and optimization on medium voltage networks. In 2014, he participated in the Marie Curie Initial Training Network Advantage-FP7 as a research engineer in the Center of Telecommunication Technology of Catalunya within the Advanced Signal and Information Processing department. Since 2014 he is pursuing his PhD in the Signal Theory and Communications department of the Polytechnic University of Catalunya. His main research activities are power system state estimation, statistical signal processing and convex optimization for smart grids. Currently, he is working within the Research and Development Department of the Greek Independent Power Transmission System Operator. His contribution to EASY-RES will be mainly focused on the activities of WP1, WP2, WP5 and WP6.